As the number of available transistors has increased, processor-chip architects have turned to multithreaded processors such as simultaneous multithreaded (SMT) processors as a way to continue to increase performance. Generally, SMT processors permit multiple threads to execute instructions using the same set of functional units within a given core. However, this means that the different hardware threads then compete for use of those functional units. One class of shared resources includes the execution units or functional units such as the integer units, floating-point units, load-store units, and the like. It is predicted that SMT processor will become a commonplace platform for the next generation of processor chips. However, because of its capability to allow sharing of processor resources, SMT technique in processors introduces a new degree of complexity in scheduling.
Currently, hardware does not provide the operating system with a capability to understand the crucial attributes of a thread on an SMT processor. The operating system may perform better job scheduling functions, for example, if it is made aware of the thread characteristics. Thus, what is needed is a method and system for the hardware and the operating system on multithreaded processors such as SMT processors to communicate information about the threads on the processors, so that for example, an operating system may utilize the information for effective scheduling.